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MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop
September 1983 Revised May 2005
MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop
General Description
The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. These devices are positive edge triggered flip-flops. Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function, and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
s Typical propagation delay: 18 ns s Wide operating voltage range: 2V-6V s Low input current: 1 PA maximum s Low quiescent current: 80 PA maximum s Compatible with bus-oriented systems s Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number MM74HC574WM MM74HC574SJ MM74HC574MTC MM74HC574N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Output Control L L L H Clock Data Output
n n
L X
H L X X
H L Q0 Z
H HIGH Level L LOW Level X Don't Care n Transition from LOW-to-HIGH Z High Impedance State Q0 The level of the output before steady state input conditions were established
Top View
(c) 2005 Fairchild Semiconductor Corporation
DS005213
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MM74HC574
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260qC 600 mW 500 mW
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN,VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC VCC VCC 2.0V 4.5V 6.0V 1000 500 400 ns ns ns 2 0 Max 6 VCC Units V V
0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r35 mA r70 mA 65qC to 150qC
40
85
qC
Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: 12 mW/qC from 65qC to 85qC.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN
(Note 4)
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 25qC TA
Conditions
40 to 85qC TA 55 to 125qC
Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4
Units
V
V
VIH or VIL 2.0V 4.5V 6.0V V
|IOUT | d 20 PA
VIN
VIH or VIL 4.5V 6.0V 2.0V 4.5V 6.0V V
|IOUT | d 6.0 mA |IOUT | d 7.8 mA VOL Maximum LOW Level Output Voltage VIN VIH or VIL |IOUT | d 20 PA
V
VIN
VIH or VIL 4.5V 6.0V 6.0V 6.0V 6.0V OE CLK DATA 1.0 0.6 0.4 V
|IOUT | d 6.0 mA |IOUT | d 7.8 mA IIN IOZ ICC Maximum Input Current Maximum 3-STATE Output Leakage Current Maximum Quiescent Supply Current Quiescent Supply Current per Input Pin VIN VOUT OC VIN IOUT VCC VIN VCC or GND VCC or GND VIH VCC or GND 0 PA 5.5V 2.4V
r0.1 r0.5
8.0 1.5 0.8 0.5
r1.0 r5.0
80 1.8 1.0 0.6
r1.0 r10
160 2.0 1.1 0.7
PA PA PA
mA
'ICC
or 0.4V (Note 4)
Note 4: For a power supply of 5V r10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC574
AC Electrical Characteristics
VCC
5V, TA
25qC, tr
tf 6 ns
Parameter Conditions Typ 60 CL RL CL RL CL 45 pF 1 k: 45 pF 1 k: 5 pF 10 12 5 15 ns ns ns 14 25 ns 17 19 Guaranteed Limit 33 27 28 Units MHz ns ns
Symbol fMAX tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tS tH tW
Maximum Operating Frequency Maximum Propagation Delay, Clock to Q Maximum Output Enable Time Maximum Output Disable Time Minimum Setup Time, Data to Clock Minimum Hold Time, Clock to Data Minimum Pulse Clock Width
3
8
AC Electrical Characteristics
VCC
2.0 6.0V, CL
50 pF, tr
tf 6 ns (unless otherwise specified)
Conditions CL 50 pF VCC 2.0V 4.5V 6.0V TA Typ 33 30 35 18 51 13 19 12 18 22 59 14 20 12 18 15 12 10 6 30 155 23 31 20 27 30 180 28 36 24 31 30 25 21 12 20 17 25qC TA
Symbol fMAX
Parameter Maximum Operating Frequency
40 to 85qC TA 55 to 125qC
Guaranteed Limits 28 24 28 38 194 29 47 25 34 38 225 35 45 30 39 38 31 27 15 25 21 6 0 0 15 15 13 20 20 18 1000 500 400 23 20 23 45 233 35 47 30 41 45 270 42 54 36 47 45 38 32 18 30 25 8 0 0 18 18 15 24 24 20 1000 500 400
Units
MHz
tPHL, tPLH
Maximum Propagation Delay, Clock to Q
CL CL CL CL CL CL
50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF
2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V
ns ns ns
tPZH, tPZL
Maximum Output Enable Time
RL CL CL CL CL CL CL
ns ns ns
tPHZ, tPLZ
Maximum Output Disable Time
RL CL
ns
tS
Minimum Setup Time Data to Clock
ns
tH
Minimum Hold Time Clock to Data
1
5 0 0
ns
tTHL, tTLH
Maximum Output Rise and Fall Time
CL
50 pF
2.0V 4.5V 6.0V 2.0V 4.5V 6.0V
6 7 6 30 9 8
12 12 10 15 16 14 1000 500 400
ns
tW
Minimum Clock Pulse Width
ns
tr,tf
Maximum Clock Input Rise and Fall Time
2.0V 4.5V 6.0V OC OC VCC GND 5 58 5
ns
CPD CIN
Power Dissipation Capacitance (Note 5) (per latch) Maximum Input Capacitance
pF 10 10 10 pF
3
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MM74HC574
AC Electrical Characteristics
Symbol COUT Parameter Maximum Output Capacitance
(Continued)
TA Typ 15 20 25qC TA
Conditions
VCC
40 to 85qC TA 55 to 125qC
Guaranteed Limits 20 20
Units pF
Note 5: CPD determines the no load dynamic power consumption, PD IS CPD V CC f ICC.
CPD VCC2 f ICC VCC, and the no load dynamic current consumption,
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MM74HC574
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
5
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MM74HC574
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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MM74HC574
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
7
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MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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